1. Field of the Invention
The present invention relates to a synchronous dynamic random access memory (SDRAM), and more particularly to a refresh circuit for an SDRAM.
2. Description of the Conventional Art
Generally, a refresh operation of a dynamic random access memory (DRAM) standard has two methods, that is a RAS (row address strobe)-only-refresh and an automatic (CAS(column address strobe)-before-RAS: CBR) refresh. The RAS-only-refresh is executed, after externally applying a refresh address, in 1 cycle in which a /RAS signal falls and then rises, and in the automatic refresh an address counter installed in a DRAM generates a predetermined internal address instead of externally applying the refresh address, thereby performing the refreshing of the DRAM.
The SDRAM which is a kind of the DRAM also requires a refreshing process and for the refresh operation of the SDRAM the automatic (CBR) refresh is set under the JEDEC standard.
FIG. 1 schematically illustrates a refresh circuit of a conventional SDRAM for performing the automatic refresh. As shown therein, the conventional refresh circuit includes: a control signal input buffer 11 outputting externally applied control signals, such as /RAS (row address strobe bar), /CAS (column address strobe bar), /WE (write enable bar) and /CS (column select bar), in accordance with an input enable clock signal (CLK.sub.-- INEN) which is applied from a clock pad 10; a command generating unit 12 generating a refresh control signal REFRCL by combining the controls signals (/RAS, /CAS, /WE, /CS) supplied from the control signal input buffer 11 and synchronizing the resultant signal with a clock signal CLK.sub.-- CMD applied from the clock pad 10; a row activating unit 13 activating a row operation in accordance with the refresh control signal REFRCL; a row activation controlling unit 14 controlling the row activating unit 13; an internal address counter 15 generating a predetermined internal address signal (HX&lt;0:k&gt;) by synchronizing with a clock signal CLK.sub.-- XA an internal address increasing signal INCHX which is activated in accordance with the refresh control signal REFRCL; a row pre-decoder 16 decoding the internal address signal (HX&lt;0:k&gt;) to a row address signal (PX&lt;0:n&gt;) of a certain bit in accordance with a control signal INTX supplied from the row activating unit 13; a wordline model signal generating unit 17 generating a wordline model signal WLMODEL in accordance with a timing when an actual wordline is activated according to the refresh control signal REFRCL and a control signal REF.sub.-- RAS of the row activation controlling unit 14; and a sense amp state predicting unit 18 generating a signal SRSUMD which indicates that a sense amp is sufficiently amplified and outputting the signal SRSUMD to the row activation controlling unit 14, when a predetermined time has elapsed after receiving the wordline model signal WLMODEL from the wordline model signal generating unit 17.
To operate the thusly configured refresh circuit of the conventional SDRAM, first, the control signal input buffer 11 which receives the externally applied /RAS, /CAS, /WE, /CS signals synchronizes the received signals with the input enable signal CLK.sub.-- INEN supplied from the clock pad 10, thereby outputting the resultant signals /RAS, /CAS, /WE, /CS, and then the command generating unit 12 which generates a command by combining logic values of the signals /RAS, /CAS, /WE, /CS generates the control signal REFRCL for performing the refresh when the signals /RAS, /CAS, /CS are respectively a low level and the signal /WE is a high level, and supplies the refresh control signal REFRCL to the row activating unit 13 and the wordline model signal generating unit 17, respectively.
When receiving the refresh control signal REFRCL, the row activating unit 13 generates and applies a signal REF.sub.-- ACT to the row activation controlling unit 14 during which the refresh is being performed, and the row activation controlling unit 14 applies the control signal REF.sub.-- RAS for respectively activating the row activating unit 13 and the wordline model signal generating unit 17 for 1 cycle of the refresh, that is the cycle during which the /RAS signal falls to the low level and again rises to the high level. The row activating unit 13 generates the control signal INTX which controls the row pre-decoder 16 to receive the internal address signal (HX&lt;0:K&gt;), the control signal INTX being supplied to the row pre-decoder 16.
While, the internal address counter 15 synchronizes the signal which is activated in accordance with the refresh control signal REFRCL, that is the internal address increasing signal INCHX for counting up the internal address by 1 bit, with the clock signal CLK.sub.-- XA in which one clock is enabled when the row activation proceeds, for thereby generating the internal address signal (HX&lt;0:K&gt;) which is supplied to the row pre-decoder 16. Then, the row pre-decoder 16 receives the internal address signal (HK&lt;0:k&gt;) in accordance with the control signal INTX of the row activating unit 13 and decodes the internal address signal (HK&lt;0:k&gt;) to the row address signal (PX&lt;0:n&gt;) of a certain bit, and accordingly the wordline which is selected by the row address signal (PX&lt;0:n&gt;) is on, so that memory cells connected with the selected wordline are refreshed.
When the wordline model signal generating unit 17 which receives the refresh control signal REFRCL of the command generating unit 12 and the control signal REF.sub.-- RAS of the row activation controlling unit 14 generates the wordline model signal WLMODEL in accordance with the timing when the actual wordline is activated, the sense amp state predicting unit 18 pulses the predetermined signal SRSUMD, when a predetermined time has elapsed after receiving the wordline model signal WLMODEL, that is the point at which the sense amp sufficiently performs the sensing operation. Thus, the row activation controlling unit 14 supplies a control signal CLR.sub.-- ACT for controlling the row activating unit 13 to reset the corresponding wordline to the row activating unit 13 which generates a reset signal (CLRX&lt;0:n&gt;) for resetting the corresponding wordline. Thus, when the above operation is repeatedly performed until whole wordlines are all selected, all of the SDRAM cells can be refreshed.
However, since the refresh of the conventional SDRAM should be performed for whole memory cells before signal charges accumulated in capacitors of memory cells are emitted and thus it becomes impossible to judge the charge as `1` or `0`, the refresh cycle becomes shortened, which results in deterioration of the system performance.
Also, in view of the system application, the refresh is performed with respect to the whole memory cells even though the SDRAM cells are only partially used, which causes a problem of consuming unnecessary electric current.